1. Field of the Invention
The invention relates to a semiconductor chip, and more particularly, to balance timing skews of a semiconductor chip.
2. Description of the Related Art
In the modern high-speed very-large-scale integrated (VLSI) circuits, clock design plays a crucial role in determining chip performance and facilitating timing and design convergence. Clock routing is important in the layout design of a synchronous system since it influences function, area, speed, and power dissipation of the synthesized system. Therefore, minimization of timing skew of clock has been a critical problem for high-performance and high-speed circuits of VLSI design.
In general, clock tree synthesis (CTS) is performed to insert buffers to reduce timing skew and to construct a clock tree to reach an optimized solution by taking timing skew, circuit-area and power-consumption into considerations. However, the timing skew of the clock tree varies quite obviously for different process, temperature and voltage corners. For advanced technology, this effect becomes even worse. One way to deal with this problem is to use the proposed semiconductor chip and packages.